Recently, a DRP (Dynamically Reconfigurable Processor) is attracting attention as an array type processor capable of easily changing a circuit behavior while achieving the performance of a dedicated logic circuit.
With the advancement of the computer technology, design, analysis, evaluation, etc. of electronic circuits realized by using a DRP are typically carried out using a CAD (Computer-Aided Design) system equipped with a behavioral synthesis tool and logic synthesis tool. For example, Unexamined Japanese Patent Application KOKAI Publication No. 2003-99409 discloses a behavioral synthesis apparatus which is adapted to such a CAD system.
The behavioral synthesis tool performs behavioral synthesis based on a behavioral level description containing information necessary for achieving a hardware configuration, such as input ports and the bit widths of variables, to output an RTL (Register Transfer Level) description.
More specifically, the behavioral synthesis tool performs syntax parsing on an behavioral level description written in a high-level language, such as System C, to generate a DFG (Data Flow Graph). The behavioral synthesis tool performs scheduling based on the generated DFG to generate a CDFG (Control Data Flow Graph). Then, the behavioral synthesis tool generates an RTL description which can be input directly to a logic synthesis tool.
Note that the behavioral synthesis tool can generate an RTL description realizing an electronic circuit which executes processes while changing over a plurality of contexts (operational states) from one to another. In this case, the behavioral synthesis tool executes behavioral synthesis in such a way that the electronic circuit includes an STC (State Transition Controller) which changes over contexts based on a clock signal or the like. There may be a single context in which case the STC changes over a plurality of processing stages (stage control states) in a single context.
To realize a fast computation circuit, a pipelined circuit is frequently used. The pipelined circuit includes a plurality of stage circuits to which different computation processes are assigned. The individual stage circuits receive data from the preceding stage circuits, perform computations in parallel at a mutually common number of clocks, and give the computation results to the subsequent stage circuits.
There are a lot of demands to achieve fast computation in realizing such a pipelined circuit with a reconfigurable semiconductor integrated circuit like a DRP.